While integrated circuit devices continue to shrink in size, the use of wet etch processes in the manufacture of CMOS (Complementary metal-oxide semiconductor) devices, for example, in Front-End Of the Line (FEOL) integration process flows, have not scaled. As a result, the size of divots, caused by the isotropic nature of wet etch, as a function of feature pitch has remained essentially flat for several generations of logic and ASIC (Application-Specific Integrated Circuit) devices.
For example, as the lateral spacing between devices decreases, divots that may be formed at the corners in narrowly spaced FET (field-effect transistor) islands will tend to merge, creating a recess in the shallow trench isolation (STI). On the other hand, where the separation between FET islands is relatively wide, the STI oxide will be relatively taller and may be left sticking up above the surface of the substrate.
For example, referring to FIG. 1, a typical process flow to form FET devices on a bulk substrate may include a wafer 100 having a first dielectric (pad) (i.e. oxide) layer 120 formed on a silicon substrate 110, and a second dielectric (e.g. nitride) layer 130 formed on the first pad oxide layer 120. Next, a patterned resist layer 140 is formed over the wafer 100, having openings 145 through which the upper surface of the wafer 100, i.e. the nitride layer 130, is exposed. Next, trenches 150 are formed in the substrate 110 by etching through the pad nitride 130, the pad oxide 120 and partially through the silicon substrate 110, for example, using an anisotropic etch, such as a reactive ion etch (RIE). The resist layer 140 may be removed, and the resulting structure is illustrated in FIG. 3.
Next, a third dielectric fill material 160 is deposited over the wafer 100, filling the trenches 150 and covering the top horizontal surfaces of the pad nitride 130. The fill oxide that covers the horizontal surfaces of the wafer is referred to as the field oxide (not shown). The third dielectric fill material 160 is preferably oxide, but may comprise other suitable dielectric materials such as poly-siloxane, polysilazane, or a combination thereof. The third dielectric fill material 160 may be deposited by any suitable method, such as spin-coating. An oxide fill material 160 may undergo a low temperature Ultraviolet (UV) cure or a high temperature thermal anneal process (for example, at temperatures above about 900° C. in N2, forming gas or steam ambient). This is followed by a planarizing step, such as chemical-mechanical polishing (CMP) to remove field oxide from the surface of the pad nitride 130 and planarize the surface of the wafer 100, while leaving the trenches 150 filled with the third dielectric fill (e.g. oxide) material 160, which form shallow trench isolation (STI) structures, as illustrated in FIG. 4.
The pad nitride layer 130 is then removed, for example by using a wet etch selective to SiO2, such as hot phosphoric acid chemistry at 160° C., leaving islands 161, 162 of oxide 160 protruding above the surface of the wafer 100 as illustrated in FIG. 5. In the example illustrated, the island 161 has a width W1 that is relatively narrow compared to the width W2 of the island 162, as defined relative to the depth d of the lateral etch. Multiple well implants (not shown for clarity) may be typically formed by implantation through the thin pad oxide layer 120, which is typically followed by the well diffusion anneals (not shown for clarity), as known in the art. Subsequently, the pad oxide layer 120 is removed, typically using a wet etch method which is isotropic and may be characterized by a lateral etch depth d, thus creating divots 165 along the corners of the oxide islands 161, as illustrated in FIG. 6.
Depending on the final application, a single chip could have multiple gate oxide thicknesses and threshold voltage (Vt) offerings. These multi-functionality requirements will typically add additional wet etch process steps, which increases the wet etch budget requirements, which in turn may lead to excessive divoting 175 in both the STI 160 and the substrate material 110, as illustrated in FIG. 7 and discussed further below.
In the case where the STI 161 has been defined relatively narrowly compared to the lateral wet etch depth d, the divots 175 may merge together, forming a recess 185, having a depth 180 below the surface of the substrate 110. On the other hand, if the STI 162 has been defined relatively widely compared to the lateral wet etch depth d, the divots 175 will etch into the substrate material 110 as well as the STI material 160, but the STI island 162 will have a top surface 172 that is relatively taller, by a height h above the top surface of the substrate 110, than the relatively narrow STI 161, as illustrated in FIG. 7. This difference in topography may continue to exist even after subsequent processing and may be challenging to remove as illustrated in FIG. 8.
This spacing-dependent topography in STI structures in critical device macros poses lithographic/RIE challenges during the gate patterning due to varying gate stack heights in the STI region resulting from the STI topography.
Prior attempts to reduce the wet etch budget have been difficult, particularly as more complex technology elements have been introduced on the same chip, such as multiple Vt and low power/high performance (i.e. having multiple gate oxide thicknesses) offerings, and the use of advanced stressor and salicidation schemes.
It would be desirable to provide a wet etch method that has a budget that scales with device size.